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1 ? DR3100 433.92 mhz transceiver module the DR3100 transceiver module is ideal for short-range wireless data applications where robust operation, small size and low power consumption are required. the DR3100 utilizes rfm?s tr3000 amplifier-sequenced hybrid (ash) architecture to achieve this unique blend of charac - teristics. the receiver section of the tr3000 is sensitive and stable. a wide dynamic range log detector provides robust performance in the presence of on-channel interference or noise. two stages of saw filtering provide excellent receiver out-of-band rejection. the transmitter includes provisions for both on-off keyed (ook) and amplitude-shift keyed (ask) modulation. the trans - mitter employs saw filtering to suppress output harmonics, facilitating compliance with etsi i-ets 300 220 and similar regulations. the DR3100 includes the tr3000 plus all configuration components in a ready-to-use pcb assembly, excellent for prototyping and intermediate volume production runs. rating value units power supply and all input/output pins -0.3 to +4.0 v non-operating case temperature -50 to +100 o c soldering temperature (10 seconds) 230 o c absolute maximum ratings designed for short-range wireless data communications supports 2.4-19.2 kbps encoded data transmissions 3 v, low current operation plus sleep mode ready to use oem module electrical characteristics, 2.4 kbps on-off keyed characteristic sym notes minimum typical maximum units operating frequency f o 433.72 434.12 mhz modulation type ook data rate 2.4 kbps receiver performance (ook @ 2.4 kbps) input current, 3 vdc supply i r 4.5 ma input signal for 10 -4 ber, 25 c -100 dbm rejection, 30 mhz r rej 55 db transmitter performance (ook @ 2.4 kbps) peak input current, 3 vdc supply i tp 12 ma peak output power p o 1.2 mw turn on/turn off time t on /t off 12/6 s sleep to receive switch time (100 ms sleep, -85 dbm signal) t sr 200 s sleep mode current i s 0.75 a transmit to receive switch time (100 ms transmit, -85 dbm signal) t tor 200 s receive to transmit switch time t rto 12 s power supply voltage range v cc 2.7 3.5 vdc operating ambient temperature t a -40 +85 o c
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pin name description 1 agc/vcc this pin is connected directly to the transceiver agccap pin. to disable agc operation, this pin is tied to vcc. to enable agc operation, a capacitor is placed between this pin and ground. this pin controls the agc reset op - eration. a capacitor between this pin and ground sets the minimum time the agc will hold-in once it is engaged. the hold-in time is set to avoid agc chattering. for a given hold-in time t agh , the capacitor value c agc is: c agc = 19.1* t agh , where t agh is in s and c agc is in pf a 10% ceramic capacitor should be used at this pin. the value of c agc given above provides a hold-in time be - tween t agh and 2.65* t agh , depending on operating voltage, temperature, etc. the hold-in time is chosen to allow the agc to ride through the longest run of zero bits that can occur in a received data stream. the agc hold-in time can be greater than the peak detector decay time, as discussed below. however, the agc hold-in time should not be set too long, or the receiver will be slow in returning to full sensitivity once the agc is engaged by noise or interference. the use of agc is optional when using ook modulation with data pulses of at least 30 s. active or latched agc operation is required for ask modulation and/or for data pulses of less than 30 s. the agc can be latched on once engaged by connecting a 150 k resistor between this pin and ground, instead of a capacitor. agc operation depends on a functioning peak detector, as discussed below. the agc capacitor is dis - charged in the transceiver power-down (sleep) mode and in the transmit modes. note that provisions are made on the circuit board to install a jumper between this pin and the junction of c2 and l3. installing the jumper allows ei - ther this pin or pin 7 to be used for the vcc supply when agc operation is not required. 2 pk det this pin is connected directly to the transceiver pkdet pin. this pin controls the peak detector operation. a ca - pacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ra - tio. for most applications, the attack time constant should be set to 6.4 ms with a 0.027 f capacitor to ground. (this matches the peak detector decay time constant to the time constant of the 0.1 f coupling capacitor c3.) a 10% ceramic capacitor should be used at this pin. the peak detector is used to drive the ?db-below-peak? data slicer and the agc release function. the agc hold-in time can be extended beyond the peak detector decay time with the agc capacitor, as discussed above. where low data rates and ook modulation are used, the ?db-below-peak? data slicer and the agc are optional. in this case, the pkdet pin can be left unconnected, and the agc pin can be connected to vcc to reduce the number of external components needed. the peak detector capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. see the descrip- tion of pin 3 below for further information. 3 rx bbo this pin is connected directly to the transceiver bbout pin. on the circuit board, bbout also drives the trans- ceiver cmpin pin through c3, a 0.1 f coupling capacitor (t bbc = 6.4 ms). rx bbo can also be used to drive an external data recovery process (dsp, etc.). the nominal output impedance of this pin is 1 k. the rx bbo signal changes about 10 mv/db, with a peak-to-peak signal level of up to 675 mv. the signal at rx bbo is riding on a 1.1 vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca - pacitor to an external load. a load impedance of 50 k to 500 k in parallel with no more than 10 pf is recom - mended. note the agc reset function is driven by the signal applied to cmpin through c3. when the transceiver is in power-down (sleep) or in a transmit mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor(s). the value of c3 on the circuit board has been chosen to match typical data encoding schemes at 2.4 kbps. if c3 is modified to support higher data rates and/or different data encoding schemes and pk det is being used, make the value of the peak detector capacitor about 1/3 the value of c3. 4 rx data rx data is connected directly to the transceiver data output pin, rxdata. this pin will drive a 10 pf, 500 k par - allel load. the peak current available from this pin increases with the receiver low-pass filter cutoff frequency. in the power-down (sleep) or transmit modes, this pin becomes high impedance. if required, a 1000 k pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance (do not connect the pull-up resistor to a supply voltage higher than 3.5 vdc or the transceiver will be damaged). this pin must be buffered to successfully drive low-impedance loads. 5txin the tx in pin is connected to the transceiver txmod pin through a 4.7 k resistor on the circuit board. additional series resistance will often be required between the modulation source and the tx in pin, depending on the de - sired output power and peak modulation voltage (4.3 k typical for a peak modulation voltage of 3 volts). saturated output power requires about 250 a of drive current. peak output power p o for a 3 vdc supply is approximately: p o = 19.75*((v txh ? 0.9)/(r m + 4.7)) 2 , where p o is in mw, peak modulation voltage v txh is in volts and external modulation resistor r m is in kilohms this pin must be held low in the receive and sleep modes. please refer to section 2.9 of the ash transceiver de - signer?s guide for additional information. 3 pin descriptions
6 gnd this is a ground pin. 7 gnd this is a ground pin. 8 lpf adj this pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the transceiver lpfadj pin. r6 on the circuit board (330 k) is connected between lpfadj and ground will be in parallel with any external re - sistor connected to lpf adj. the filter bandwidth is set by the parallel resistance of r6 and the external resistor (if used). the equivalent resistor value can range from 330 k to 820 ohms, providing a filter 3 db bandwidth f lpf from 4.4 khz to 1.8 mhz. the 3 db filter bandwidth is determined by: f lpf = 1445/ (330*r lpf /(330 + r lpf )), where r lpf is in kilohms, and f lpf is in khz a 5% resistor should be used to set the filter bandwidth. this will provid ea3db filter bandwidth between f lpf and 1.3* f lpf with variations in supply voltage, temperature, etc. the filter provides a three-pole, 0.05 degree equiripple phase response. the peak drive current available from rxdata increases in proportion to the filter bandwidth setting. as shipped, the transceiver module is set up for nominal 2.4 kbps operation. an external resis - tor can be added between pin 6 and ground to support higher data rates. preamble training times will not be decreased, however, unless c3 is replaced with a smaller capacitor value (see the descriptions of pins 2 and 3 above). refer to sections 1.4.3, 2.5.1 and 2.6.1 in the ash transceiver designer?s guide for additional informa - tion on data rate adjustments. 9 vcc this is the positive supply voltage pin for the module. the operating voltage range is 2.7 to 3.5 vdc. it is also pos - sible to use pin 1 as the vcc input. please refer to the pin 1 description above. 10 gnd this is the supply voltage return pin. 11 ctr1 ctr1 is connected to the cntrl1 control pin on the transceiver. ctr1 and ctr0 select the transceiver operat - ing modes. ctr1 and ctr0 both high place the unit in the receive mode. ctr1 and ctr0 both low place the unit in the power-down (sleep) mode. ctr1 high and ctr0 low place the unit in the ask transmit mode. ctr1 low and ctr0 high place the unit in the ook transmit mode. ctr1 is a high-impedance input (cmos compatible). this pin must be held at a logic level; it cannot be left unconnected. at turn on, the voltage on this pin and ctr0 should rise with vcc until vcc reaches 2.7 vdc (receive mode). thereafter, any mode can be selected. 12 ctr0 ctr0 is connected to the cntrl0 control pin on the transceiver ctr0 is used with ctr1 to control the operating modes of the transceiver. ctr0 is a high-impedance input (cmos compatible). this pin must be held at a logic level; it cannot be left unconnected. at turn on, the voltage on this pin and ctr1 should rise with vcc until vcc reaches 2.7 vdc (receive mode). thereafter, any mode can be selected. 13 rfio rfio is the rf input/output pin. a matching circuit for a 50 ohm load (antenna) is implemented on the circuit board between this pin and the transceiver saw filter transducer. 14 rf gnd this pin is the rf ground (return) to be used in conjunction with the rfio pin. for example, when connecting the transceiver module to an external antenna, the coaxial cable ground is connected this pin and the coaxial cable center conductor is connected to rfio. 4
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item reference description value quantity 1 ic1 tr3000 ash transceiver 433.92 mhz 1 2 c1, c2, c4, c6 capacitor smt 0603 100 pf 10% 4 3 c3 capacitor smt 0603 0.1 f 10% 1 4 c5 capacitor e1a-b 0805 4.7 f 10% 1 5 r1 resistor chip 0603 270 k 5% 1 6r2 resistor chip 0603 330 k 5% 1 7 r3 resistor chip 0603 10 k 1% 1 8 r4 resistor chip 0603 100 k 1% 1 9 r5 resistor chip 0603 4.7 k 5% 1 10 r6 resistor chip 0603 330 k 5% 1 11 r7 resistor chip 0603 zero ohm jumper 1 12 r8 not used n/a 0 13 l1 inductor chip 0805cs 56 nh 5% 1 14 l2 inductor chip 0805cs 180 nh 10% 1 16 pcb printed circuit board 400-1526-001x1 1 5 DR3100 bill of materials note: specifications subject to change without notice. file: DR3100i.vp, 2002.10.23 rev

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